The present invention relates generally to integrated circuit memory devices and, more particularly, to a method and system for integrating SRAM and DRAM architecture in a set associative cache.
Memory devices are used in a wide variety of applications, including computer systems. Computer systems and other electronic devices containing a microprocessor or similar device typically include system memory, which is generally implemented using dynamic random access memory (DRAM). A DRAM memory cell generally includes, as basic components, an access transistor (switch) and a capacitor for storing a binary data bit in the form of an electrical charge. Typically, a first voltage is stored on the capacitor to represent a logic high or binary “1” value (e.g., VDD), while a second voltage on the storage capacitor represents a logic low or binary “0” value (e.g., ground). A principal advantage of DRAM is that it uses relatively few components to store each bit of data, and is thus a relatively inexpensive means for providing system memory having a relatively high capacity.
One disadvantage of DRAM, however, is that the individual DRAM memory cells must be periodically refreshed as the charge on the capacitor eventually leaks away and therefore provisions must be made to “refresh” the capacitor charge. Otherwise, the data bit stored by the memory cell is lost. While an array of memory cells is being refreshed, it cannot be accessed for a read or a write memory access. The need to refresh DRAM memory cells does not present a significant problem in most applications; however, it can prevent the use of DRAM in applications where immediate access to memory cells is required or highly desirable.
On the other hand, a static random access memory (SRAM) cell does not require a refresh of the data stored therein, so long as power to the device remains on. However, whereas an SRAM is typically implemented using six transistors for example, a DRAM cell uses just a single transistor and a capacitor as indicated above. The SRAM cell is therefore less dense than the DRAM cell, requiring more area per bit of storage. On the other hand, the SRAM cell is faster to access (due to the time required to charge and discharge the DRAM capacitor, as well as the need to refresh the DRAM cell at regular intervals). Accordingly, a memory having the density characteristics of DRAM with the access latency of SRAM would be preferable to either base technology.
Although a number of memory designs have been proposed and implemented in an attempt to provide the density of DRAM with the latency of SRAM, most of these take the form of incorporating an SRAM cache in an otherwise standard DRAM array, such that the SRAM holds the contents of the most recently accessed DRAM data block. To the extent that the same block of data is soon referenced again, it can be accessed at SRAM speeds. However, these approaches involve significant overhead in area and control circuitry, as well as significant design effort for new facilities.